This article discusses edge detectors implemented in programmable logic controllers.\nThe behaviors of different vendorsâ?? solutions are presented with pros and cons. The trigger functions\ndefined in the IEC 61131-3 standard were analyzed for implementations. The main contribution\nof this paper is an idea for hardware acceleration of standard trigger functions that enables us to\nbuild single-clock-cycle edge detectors. Additionally, the structure for automatic edge detection\non every input is shown. The structure with a synthesizable Verilog HDL description is presented.\nThe comparison of the solution with vendor programmable logic controllers (PLCs) proves the\neffectiveness of the designed hardware-aided unit.
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